Before telling you about the new U54-MC, let me introduce you to the basics of RISC-V CPUs. The traditional Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC) do justice to their names and focus on the difficulty level of instructions as well as optimizations.
On the other hand, the RISC-V architecture is a free and open source ISA for processors, which can be produced or implemented by anyone, for free. ISA stands for Instruction Set Architecture and tells what a CPU needs to do.
Coming back to the latest development, U45-MC Coreplex takes RISC-V commercially into Linux processing applications. It has four U54 CPUs and a single E51 CPU; each of them run at 1.5GHz. U54 cores support the RV64GC ISA, which is expected to become standard ISA for RISC-V Linux devices.
SiFive is offering customers 100 prototype SoCs for $100,000, according to EETimes. The customers don’t need to provide any fee on third-party IP until the chips are shipped. U54-MC Coreplex also comes with a rich SDK with demo software. Currently, Microsemi and Arduino are the two announced customers of SiFive.
In 2018 Q1, U54-MC will be available with a development board. Currently, it’s available in a limited “early access” phase. Find more information on SiFive’s website.
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