The PCI-SIG Developers Conference 2022 is underway. The standards committee behind the universal PCIe interface announced today that PCIe 7.0 will release for the members in 2025 and features some amazing specs.
The high-speed serial computer expansion bus standard will feature a 128 GT/s date rate of 512 GB/s of bi-directional throughput by a 16-lane (x16) connection before the encoding overhead.
For a reminder, the PCI-SG is the confederation behind the PCIe interface, an open industry standard with more than 900 member companies.
As per the PCI-SIG notes, the PCIe 7.0 interface will offer a blazing 512 GB/s of bi-directional throughput on an x16 connection; however, that is before the encoding overhead and the effect of header efficiency as both of them can influence the usable bandwidth.
The new interface will keep using the 1b/1b flit mode encoding with the PAM4 signaling tech announced with PCIe 6.0, which is a substantial improvement to the 128b/130b encoding and NRZ signaling that we saw in 3.0 to 5.0 specifications. The real-world usable bandwidth will be less than the 512 GB.s, although it still expresses the double over the PCIe 6.0 interface.
The PCIe trace length will decrease because of the faster signaling rates. The minimum distance allowed without requiring extra components between PCIe roots devices such as the CPU and end devices like GPU will reduce. Hence, motherboards will require additional retimes and thicker PCBs that contain higher quality materials than the previous gens of the interface. However, the PCIe 7.0 will contribute to another motherboard price hike.
The higher bandwidth of each lane (32 GB/s bi-directional for an x1 connection) could now let ‘thinner’ connections for certain devices (for instance, using an x4 instead of an x8 connection)
Although the PCIe 7.0 interface will be out till 2025, the devices might not roll out till 2028, which is the expected time frame when the device hits markets.
PCIe 7.0 Specs Goals
The PCI-SIG Developers Conference 2022 is underway. The standards committee behind the universal PCIe interface announced today that PCIe 7.0 will release for the members in 2025 and features some amazing specs.
The high-speed serial computer expansion bus standard will feature a 128 GT/s date rate of 512 GB/s of bi-directional throughput by a 16-lane (x16) connection before the encoding overhead.
For a reminder, the PCI-SG is the confederation behind the PCIe interface, an open industry standard with more than 900 member companies.
As per the PCI-SIG notes, the PCIe 7.0 interface will offer a blazing 512 GB/s of bi-directional throughput on an x16 connection; however, that is before the encoding overhead and the effect of header efficiency as both of them can influence the usable bandwidth.
The new interface will keep using the 1b/1b flit mode encoding with the PAM4 signaling tech announced with PCIe 6.0, which is a substantial improvement to the 128b/130b encoding and NRZ signaling that we saw in 3.0 to 5.0 specifications. The real-world usable bandwidth will be less than the 512 GB.s, although it still expresses the double over the PCIe 6.0 interface.
The PCIe trace length will decrease because of the faster signaling rates. The minimum distance allowed without requiring extra components between PCIe roots devices such as the CPU and end devices like GPU will reduce.
Hence, motherboards will require additional retimers and thicker PCBs that contain higher quality materials than the previous gens of the interface. However, the PCIe 7.0 will contribute to another motherboard price hike.
The higher bandwidth of each lane (32 GB/s bi-directional for an x1 connection) could now let ‘thinner’ connections for certain devices (for instance, using an x4 instead of an x8 connection)
Although the PCIe 7.0 interface will be out till 2025, the devices might not roll out till 2028, which is the expected time frame when the device hits markets.
PCIe 7.0 Specs Goals
- Supplying 128 GT/s raw bit rate and more than 512 GB/s bi-directionally through x16 configuration
- Using Pulse Amplitude Modulation with 4 levels (PAM4) signaling
- Concentrating on channel parameters and the reach
- Keep providing high-reliability and low-latency targets.
- Improving the power efficiency
- Preserving backward compatibility with the previous generations
- Supplying 128 GT/s raw bit rate and more than 512 GB/s bi-directionally through x16 configuration
- Using Pulse Amplitude Modulation with 4 levels (PAM4) signaling
- Concentrating on channel parameters and the reach
- Keep providing high-reliability and low-latency targets.
- Improving the power efficiency
- Preserving backward compatibility with the previous generations
